Flat panel displays (hereinafter abbreviated as FPDs) such as liquid-crystal and plasma display panels are being commonly used as display apparatuses. Video signals (pixel signals), each corresponding to a single pixel, are provided to an FPD to display images. Specifically, video signals to be provided to the FPD are temporarily held in a display memory and the FPD reads pixel signals corresponding to pixels of the FPD from the display memory and drives the pixels to display an image.
Accordingly, horizontal and vertical synchronization signals used for display on the FPD (hereinafter referred to as display horizontal and vertical synchronization signals, respectively) are generated asynchronously to horizontal and vertical synchronization signals of video signals (input video signals) provided to the FPD (hereinafter referred to as input horizontal and vertical synchronization signals).
The frequency of the display vertical synchronization signal for the FPD (hereinafter referred to as display vertical synchronization frequency) relates to the reciprocal of a cycle period of vertical synchronization signal, is determined by a display clock, a horizontal synchronization period, and a vertical synchronization period, and is a value specific to each individual display apparatus. Another value specific to each individual display apparatus is an allowable range of vertical synchronization cycle period. The provision of the range between a minimum vertical synchronization period (Vsht) and a maximum vertical synchronization period (Vlng) (hereinafter the range will be referred to as a compensation period) enables the FPD to constantly provide a display based on input video signals.
As has been described, the display vertical synchronization frequency can vary from one FPD to another and the frequency of the input vertical synchronization signal of an input video signal (hereinafter referred to as input vertical synchronization frequency) can also vary from one vide source to another. Usually, the display and input vertical synchronization frequencies are not equal to each other.
If for example the input vertical synchronization frequency is higher than the display vertical synchronization frequency, a display memory overflow can occur. To prevent an overflow, the display apparatus skips video signals of one frame and reads and uses video signals of a next frame to provide a display. On the other hand, if the input vertical synchronization frequency is lower than the display vertical synchronization frequency, a display memory underflow can occur. To prevent an underflow, the display apparatus repeats a read of video signals of one frame to repeat a display.
In this way, video signals can be skipped or repeated at certain intervals due to a difference between the input vertical synchronization frequency and the display vertical synchronization frequency in the FPD, which degrades the display quality of the FPD. Furthermore, if the display vertical synchronization signal is simply synchronized to the input vertical synchronization signal, a display synchronization frequency that enables display cannot be obtained due to variations in the input vertical synchronization frequency of the same channel, input vertical frequency phase shifting or a difference between frequencies at a timing of input video signal switching at switching from one channel to another.
To address the problem, Japanese Patent Application Laid-Open Publication No. 11-331638 (hereinafter referred to as Document 1) proposes a synchronization control circuit that synchronizes a display vertical synchronization signal to an input vertical synchronization signal. In the proposal, after a start point of vertical synchronization of an input video signal falls in a compensation period allowed in a display apparatus, processing is performed to synchronize the display vertical synchronization signal to the input vertical synchronization signal, thereby preventing occurrence of skip and repeat of video signals.
However, the proposal in Document 1 has a problem that the synchronization takes relatively long time depending on a phase difference and frequency difference between the display vertical synchronization signal and the input vertical synchronization signal. An FPD may display images from a video game machine. In that case, it is desirable that a delay time between an input image and a display image be minimized. The proposal has another problem that one skip needs to be caused for synchronization.